1. Field of the Invention
The present invention relates generally to programmable logic array devices and more particularly to an erasable, electrically programmable logic device made using CMOS EPROM Floating Gate technology.
2. Discussion of the Technology and Prior Art
The integrated circuit technology used in the fabrication of the present invention is CMOS Floating Gate (CMOS EPROM). Floating gate technology allows "programming" of certain transistors such that when normal operating voltages are applied (0 to 5 volts) the "programmed" transistor acts like an open circuit. In their unprogrammed state, these same transistors will conduct when 5 volts is applied to the gate terminal and will appear as an open circuit when 0 volts is applied to the gate terminal.
In the past, the normal application of the technology was to manufacture electrically programmable read only memories (EPROM). The programmable element in EPROM technology is a two layer polysilicon MOS transistor. By changing the circuits which access the array of programmable elements, programmable logic arrays (PLA) can be realized. Prior art U.S. patents include U.S. Pat. Nos.: Kahng, 3,500,142, Frohman-Bentchkowsky, 3,660,819; Frohman-Bentchkowsky, 3,728,695; Frohman-Bentchkowsky, 3,744,036; Frohman-Bentchkowsky, 3,755,721; Frohman-Bentchkowsky, 3,825,946; Simko et al, 3,984,822; and Lohstroh et al, 4,019,197.
Programmable logic arrays and similar circuit elements such as programmable array logic (PAL) have been in existence for many years. See for example, the U.S. Patents to: Crawford et al, U.S. Pat. No. 3,541,543; Spenser, Jr., U.S. Pat. No. 3,566,153; Proebsting, U.S. Pat. No. 3,702,985; Greer, U.S. Pat. No. 3,816,725; Greer, U.S. Pat. No. 3,818,452; Greer, U.S. Pat. No. 3,849,638. The first realizations were mask programmed. An example is a P channel MOS device manufactured by Texas Instruments during 1968-1970.
More recently, the techology of choice has been fuse programmable bipolar technology made by manufacturers such as Signetics, Monolithic Memories, Inc., Advanced Micro Devices, Harris Semiconductor and others.
The complexity of PLAs and PALs is given in terms of:
(a) The number of Inputs; PA1 (b) The number of Product Terms in the AND array; PA1 (c) The number of Sum Terms in the OR array; PA1 (d) The number of Storage Elements (FLip Flops); PA1 (e) The number of Feedback lines from the output of the OR array (or the Flip Flops) to the AND array; and PA1 (f) The number of Outputs. PA1 (a) 10 Inputs (from off chip) to the AND array; PA1 (b) 74 Product Terms (P-Terms); PA1 (c) 8 Sum Terms (Fixed OR Structure with 8 P-Terms each); PA1 (d) 8 D type Flip Flops; PA1 (e) 8 Feedback lines; and PA1 (f) 8 Outputs. PA1 (a) One of the inputs (Pin #1) to the AND array also serves as the CLOCK to the D Flip Flops; PA1 (b) The P-Terms are grouped as follows: PA1 (c) Each of the Sum Terms from the OR/NOR gate can be either "active high" or "active low"; PA1 (d) The I/O pins can output either combinatorial data (active high or active low) or registered data from the D flip flops (active high or active low); PA1 (e) Feedback can be from one of the following three data sources; the I/O pins, the output of the register, the output of the OR gate; PA1 (f) Selection of output data and feedback data is made by programming EPROM transistors in the Architectural Feature Select Section; PA1 (g) EPROM transistors are used for all programmable elements. Thus, the device is electrically programmable and UV erasable. PA1 (a) Greater logic density (more logic in less board area); and PA1 (b) Lower system power